There are numerous protocols used to communicate information among digital devices. For example, various protocols and systems have been developed for communications among central processing units and associated chip sets, as well as with peripheral devices, such as network interface cards, storage adaptors, graphics cards, and other devices. One protocol which has been developed for transporting computer bus protocols is the PCI-Express (PCIe) protocol.
The PCI-Express protocol provides for a high bandwidth, serialized, full-duplex, point-to-point data communication link. The links are generally used to connect central processing units (CPUs) and chipsets with peripheral devices such as described above. The Peripheral Component Interconnect Special Interest Group (PCI-SIG) defines the specifications for compliance to the PCIe standards.
Rather than use a bus, PCIe systems provide point-to-point full duplex data lanes. A single link may consist of from 1 to 32 lanes. The data rate on each lane is determined by the characteristics of that electrical connection. The connection characteristics are reflected in the PCIe generation specification. PCIe 1.1 provides 2.5 gigabits per second (Gb/s) per lane, PCIe 2 provides 5.0 gigabits per second per lane, and PCIe 3 provides 8 gigabits per second per lane. In a typical computer system each slot carries one, two, four, eight, or sixteen lanes of data between a motherboard and an associated card, usually plugged into a socket on the motherboard. Sixteen lanes of 5.0 Gb/s provides a maximum transfer rate of 80Gb/s (5.0 Gb/s×16) in each direction for PCIe 2.0. After encoding, the raw throughput of a lane is 80% of the data rate. Faster generations require support of the slower rates, and links auto-negotiate the lane speed and number of lanes (link width), according to the capabilities of the devices at each end of the link.
To support the data lanes, the PCIe system provides a set of supporting auxiliary signals, including a clock lane and signals for system control, such as reset, hot plug, and power management. The system also requires a state machine that controls the state of the link, such as the data rate of the lanes, the link width, the power level of the link, and other factors.
The PCI-SIG has specified the base specification which defines PCIe architecture, signaling, protocol and software. It also includes a PCIe Card Electromechanical specification defining interface form factors, as well as a PCIe External Cabling specification which defines connectors and cables for external interfaces. There is currently no specification or standard for transporting the PCIe protocol over optical links.
An array of products exist based on the PCIe standard. These include products designed for direct integration onto personal computer and server computer motherboards, PCIe cards, and other PCIe standard and non-standard form factors.
A standard known as ‘PCIe External Cabling Specification Revision 0.9’ was released by the PCI-SIG in September, 2006. This specification defines the logical, electrical, and mechanical characteristics of a standards-compliant PCIe copper cabled implementation. This specification supports PCIe 1 signaling only, and a similar specification for PCIe 2 is expected from the PCI-SIG in the future. For higher data rates such as PCIe 2, the reach on such cables is expected to be reduced.
Optical communication links are well known for some technologies. These include Fibre Channel, InfiniBand, and 10 Gigabit Ethernet (10GbE) among others. Sun Microsystems sells an “External I/O Expansion Unit” which implements an optical link emulation of a PCIe bus. All of these optical links and products, however, do not support PCIe-specific features such as sideband lane and encoding, hot plug, receiver detect, electrical idle support, linear clock lane, and others. Some parallel optical links exist, both proprietary and multi-source agreement (MSA) based. These modules, however, suffer from the same disadvantages as the optical communication links and products discussed above, notably they do not support PCIe specific features such as sideband lane and encoding, hot plug, receiver detect, electrical idle support, linear clock lane, and others.